Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit Interactions
Ferroelectric transistors (FeFETs)-based crossbar arrays have shown immense promise for computing-in-memory (CiM) architectures targeted for neural accelerator designs. Offering CMOS compatibility, nonvolatility, compact bit cell, and CiM-amenable features, such as multilevel storage and voltage-dri...
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IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10756727/ |
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| author | Chunguang Wang Sumeet Kumar Gupta |
| author_facet | Chunguang Wang Sumeet Kumar Gupta |
| author_sort | Chunguang Wang |
| collection | DOAJ |
| description | Ferroelectric transistors (FeFETs)-based crossbar arrays have shown immense promise for computing-in-memory (CiM) architectures targeted for neural accelerator designs. Offering CMOS compatibility, nonvolatility, compact bit cell, and CiM-amenable features, such as multilevel storage and voltage-driven conductance tuning, FeFETs are among the foremost candidates for synaptic devices. However, device and circuit nonideal attributes in FeFETs-based crossbar arrays cause the output currents to deviate from the expected value, which can induce error in CiM of matrix-vector multiplications (MVMs). In this article, we analyze the impact of ferroelectric thickness (<inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula>) and cross-layer interactions in FeFETs-based synaptic crossbar arrays accounting for device-circuit nonidealities. First, based on a physics-based model of multidomain FeFETs calibrated to experiments, we analyze the impact of <inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula> on the characteristics of FeFETs as synaptic devices, highlighting the connections between the multidomain physics and the synaptic attributes. Based on this analysis, we investigate the impact of <inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula> in conjunction with other design parameters, such as number of bits stored per device (bit slice), wordline (WL) activation schemes, and FeFETs width on the error probability, area, energy, and latency of CiM at the array level. Our results show that FeFETs with <inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula> around 7 nm achieve the highest CiM robustness, while FeFETs with <inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula> around 10 nm offer the lowest CiM energy and latency. While the CiM robustness for bit slice 2 is less than bit slice 1, its robustness can be brought to a target level via additional design techniques, such as partial wordline activation and optimization of FeFETs width. |
| format | Article |
| id | doaj-art-6f55ad1becf44b55bff864c01700ebcb |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-6f55ad1becf44b55bff864c01700ebcb2025-01-17T00:00:33ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-011014415210.1109/JXCDC.2024.350205310756727Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit InteractionsChunguang Wang0https://orcid.org/0009-0001-1275-0680Sumeet Kumar Gupta1https://orcid.org/0000-0001-5609-9722Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USAElmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USAFerroelectric transistors (FeFETs)-based crossbar arrays have shown immense promise for computing-in-memory (CiM) architectures targeted for neural accelerator designs. Offering CMOS compatibility, nonvolatility, compact bit cell, and CiM-amenable features, such as multilevel storage and voltage-driven conductance tuning, FeFETs are among the foremost candidates for synaptic devices. However, device and circuit nonideal attributes in FeFETs-based crossbar arrays cause the output currents to deviate from the expected value, which can induce error in CiM of matrix-vector multiplications (MVMs). In this article, we analyze the impact of ferroelectric thickness (<inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula>) and cross-layer interactions in FeFETs-based synaptic crossbar arrays accounting for device-circuit nonidealities. First, based on a physics-based model of multidomain FeFETs calibrated to experiments, we analyze the impact of <inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula> on the characteristics of FeFETs as synaptic devices, highlighting the connections between the multidomain physics and the synaptic attributes. Based on this analysis, we investigate the impact of <inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula> in conjunction with other design parameters, such as number of bits stored per device (bit slice), wordline (WL) activation schemes, and FeFETs width on the error probability, area, energy, and latency of CiM at the array level. Our results show that FeFETs with <inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula> around 7 nm achieve the highest CiM robustness, while FeFETs with <inline-formula> <tex-math notation="LaTeX">$T_{\text {FE}}$ </tex-math></inline-formula> around 10 nm offer the lowest CiM energy and latency. While the CiM robustness for bit slice 2 is less than bit slice 1, its robustness can be brought to a target level via additional design techniques, such as partial wordline activation and optimization of FeFETs width.https://ieeexplore.ieee.org/document/10756727/Computing-in-memory (CiM)crossbar arrayerror probabilityferroelectric thicknessferroelectric transistors |
| spellingShingle | Chunguang Wang Sumeet Kumar Gupta Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit Interactions IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Computing-in-memory (CiM) crossbar array error probability ferroelectric thickness ferroelectric transistors |
| title | Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit Interactions |
| title_full | Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit Interactions |
| title_fullStr | Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit Interactions |
| title_full_unstemmed | Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit Interactions |
| title_short | Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit Interactions |
| title_sort | ferroelectric transistor based synaptic crossbar arrays the impact of ferroelectric thickness and device circuit interactions |
| topic | Computing-in-memory (CiM) crossbar array error probability ferroelectric thickness ferroelectric transistors |
| url | https://ieeexplore.ieee.org/document/10756727/ |
| work_keys_str_mv | AT chunguangwang ferroelectrictransistorbasedsynapticcrossbararraystheimpactofferroelectricthicknessanddevicecircuitinteractions AT sumeetkumargupta ferroelectrictransistorbasedsynapticcrossbararraystheimpactofferroelectricthicknessanddevicecircuitinteractions |