RAPID: Redundancy Analysis With Parallelized and Intelligent Distribution
The continuous progress in semiconductor technology, particularly in nanotechnology, has led to smaller memory cells and increased fault frequency due to their proximity. These faults reduce memory yield and raise production costs. Redundancy Analysis (RA) offers an effective solution by allocating...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10818484/ |
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| Summary: | The continuous progress in semiconductor technology, particularly in nanotechnology, has led to smaller memory cells and increased fault frequency due to their proximity. These faults reduce memory yield and raise production costs. Redundancy Analysis (RA) offers an effective solution by allocating spare cells within memory to repair faulty lines. The main goal of RA is to optimally place spare cells rapidly to achieve the highest repair rate, resulting in the development of various RA methods. In modern memory architectures, complex spare structures are essential for improving repair rates. However, traditional RA methods can be too time-consuming for such structures, limiting the repair of multiple memories. This paper proposes a method called RAPID, which leverages GPU technology for the parallel repair of multiple memories. RAPID generates repair cases by segmenting areas based on available spare types, ensuring efficient GPU memory use and enabling simultaneous repairs. Repair cases are applied immediately upon fault detection during testing, significantly reducing repair time. Experimental results show that RAPID can repair more memory units in less repair time than previous GPU-based RA methods under the same GPU and CPU memory specifications. |
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| ISSN: | 2169-3536 |