The Big Chip: Challenge, model and architecture

The Big Chip: Challenge, model and architecture

As Moore’s Law comes to an end, the implementation of high-performance chips through transistor scaling has become increasingly challenging. To improve performance, increasing the chip area to integrate more transistors has become an essential approach. However, due to restrictions such as the maxim...

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Bibliographic Details
Main Authors: Yinhe Han, Haobo Xu, Meixuan Lu, Haoran Wang, Junpei Huang, Ying Wang, Yujie Wang, Feng Min, Qi Liu, Ming Liu, Ninghui Sun
Format: Article
Language:English
Published: KeAi Communications Co. Ltd. 2024-11-01
Series:Fundamental Research
Subjects:
Big Chip
Integrated chips
Area-wall
Chiplet
Performance model
Online Access:http://www.sciencedirect.com/science/article/pii/S2667325823003709
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