The Big Chip: Challenge, model and architecture
As Moore’s Law comes to an end, the implementation of high-performance chips through transistor scaling has become increasingly challenging. To improve performance, increasing the chip area to integrate more transistors has become an essential approach. However, due to restrictions such as the maxim...
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| Main Authors: | , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
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KeAi Communications Co. Ltd.
2024-11-01
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| Series: | Fundamental Research |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2667325823003709 |
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| author | Yinhe Han Haobo Xu Meixuan Lu Haoran Wang Junpei Huang Ying Wang Yujie Wang Feng Min Qi Liu Ming Liu Ninghui Sun |
| author_facet | Yinhe Han Haobo Xu Meixuan Lu Haoran Wang Junpei Huang Ying Wang Yujie Wang Feng Min Qi Liu Ming Liu Ninghui Sun |
| author_sort | Yinhe Han |
| collection | DOAJ |
| description | As Moore’s Law comes to an end, the implementation of high-performance chips through transistor scaling has become increasingly challenging. To improve performance, increasing the chip area to integrate more transistors has become an essential approach. However, due to restrictions such as the maximum reticle area, cost, and manufacturing yield, the chip’s area cannot be continuously increased, and it encounters what is known as the “area-wall”. In this paper, we provide a detailed analysis of the area-wall and propose a practical solution, the Big Chip, as a novel chip form to continuously improve performance. We introduce a performance model for evaluating Big Chip and discuss its architecture. Finally, we derive the future development trends of the Big Chip. |
| format | Article |
| id | doaj-art-68f2aa9fe7f148a69b32a1afd6c3bb0a |
| institution | Kabale University |
| issn | 2667-3258 |
| language | English |
| publishDate | 2024-11-01 |
| publisher | KeAi Communications Co. Ltd. |
| record_format | Article |
| series | Fundamental Research |
| spelling | doaj-art-68f2aa9fe7f148a69b32a1afd6c3bb0a2024-12-01T05:08:51ZengKeAi Communications Co. Ltd.Fundamental Research2667-32582024-11-014614311441The Big Chip: Challenge, model and architectureYinhe Han0Haobo Xu1Meixuan Lu2Haoran Wang3Junpei Huang4Ying Wang5Yujie Wang6Feng Min7Qi Liu8Ming Liu9Ninghui Sun10Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; University of Chinese Academy of Sciences, Beijing 100190, China; Zhejiang Lab, Hangzhou 311100, ChinaCorresponding authors.; Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, ChinaInstitute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; University of Chinese Academy of Sciences, Beijing 100190, ChinaInstitute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; University of Chinese Academy of Sciences, Beijing 100190, ChinaInstitute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; University of Science and Technology of China, Hefei 230026, ChinaInstitute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; University of Chinese Academy of Sciences, Beijing 100190, ChinaInstitute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; University of Chinese Academy of Sciences, Beijing 100190, China; Zhejiang Lab, Hangzhou 311100, ChinaInstitute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, ChinaFudan University, Shanghai 200433, ChinaFudan University, Shanghai 200433, ChinaInstitute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; University of Chinese Academy of Sciences, Beijing 100190, China; Corresponding authors.As Moore’s Law comes to an end, the implementation of high-performance chips through transistor scaling has become increasingly challenging. To improve performance, increasing the chip area to integrate more transistors has become an essential approach. However, due to restrictions such as the maximum reticle area, cost, and manufacturing yield, the chip’s area cannot be continuously increased, and it encounters what is known as the “area-wall”. In this paper, we provide a detailed analysis of the area-wall and propose a practical solution, the Big Chip, as a novel chip form to continuously improve performance. We introduce a performance model for evaluating Big Chip and discuss its architecture. Finally, we derive the future development trends of the Big Chip.http://www.sciencedirect.com/science/article/pii/S2667325823003709Big ChipIntegrated chipsArea-wallChipletPerformance model |
| spellingShingle | Yinhe Han Haobo Xu Meixuan Lu Haoran Wang Junpei Huang Ying Wang Yujie Wang Feng Min Qi Liu Ming Liu Ninghui Sun The Big Chip: Challenge, model and architecture Fundamental Research Big Chip Integrated chips Area-wall Chiplet Performance model |
| title | The Big Chip: Challenge, model and architecture |
| title_full | The Big Chip: Challenge, model and architecture |
| title_fullStr | The Big Chip: Challenge, model and architecture |
| title_full_unstemmed | The Big Chip: Challenge, model and architecture |
| title_short | The Big Chip: Challenge, model and architecture |
| title_sort | big chip challenge model and architecture |
| topic | Big Chip Integrated chips Area-wall Chiplet Performance model |
| url | http://www.sciencedirect.com/science/article/pii/S2667325823003709 |
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