Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source
The comparator plays a vital role in analog-to-digital converters. In the emerging communication era, these converters are useful to connect the analog field to the digital field. Also, the upcoming IoT-enabled portable devices have a requirement of energy-efficient high-speed conversions at low pow...
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| Format: | Article |
| Language: | English |
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Wiley
2024-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/jece/5040240 |
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| author | Tejender Singh Suman Lata Tripathi |
| author_facet | Tejender Singh Suman Lata Tripathi |
| author_sort | Tejender Singh |
| collection | DOAJ |
| description | The comparator plays a vital role in analog-to-digital converters. In the emerging communication era, these converters are useful to connect the analog field to the digital field. Also, the upcoming IoT-enabled portable devices have a requirement of energy-efficient high-speed conversions at low power consumption for a longer battery lifetime. In this paper, a double-tail dynamic latch CMOS comparator (DTDLC) with a modified Widlar current source (MWCS) has been proposed that will be suitable for high-speed applications at a low voltage and low power consumption. Use of MWCS reduces random offset voltages to avoid transistor mismatch along with the reduced power dissipation due to low operating voltage. Here, the design simulation method includes Corner analysis for power consumption and Monte Carlo histogram analysis for transistor mismatch at different random offset voltages. All the design blocks were verified and simulated by Cadence’s virtuoso schematic editor with a TSMC model file at 45-nm technology by applying 500 mV and 1 V of the supply voltage. The proposed design has a transient power consumption of 41 nW, static power consumption of 17 nW, total delay of 1 ns, and power delay product (PDP) as 17 with a FOM of 1.83 (fJ/D). By using the proposed optimized design, a total of 80% power dissipation reduction was observed. Therefore, the proposed design is more efficient in terms of metrics like delay, power, and PDP at reduced offset voltage variations and reduced effect of process variations when compared to other existing comparators. The proposed comparator circuit is also simulated and verified through layout at 45-nm CMOS process technology. |
| format | Article |
| id | doaj-art-62c886039f144bd1a0858fae7ab0a27c |
| institution | Kabale University |
| issn | 2090-0155 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-62c886039f144bd1a0858fae7ab0a27c2024-12-27T00:00:17ZengWileyJournal of Electrical and Computer Engineering2090-01552024-01-01202410.1155/jece/5040240Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current SourceTejender Singh0Suman Lata Tripathi1VLSI Design LaboratoryVLSI Design LaboratoryThe comparator plays a vital role in analog-to-digital converters. In the emerging communication era, these converters are useful to connect the analog field to the digital field. Also, the upcoming IoT-enabled portable devices have a requirement of energy-efficient high-speed conversions at low power consumption for a longer battery lifetime. In this paper, a double-tail dynamic latch CMOS comparator (DTDLC) with a modified Widlar current source (MWCS) has been proposed that will be suitable for high-speed applications at a low voltage and low power consumption. Use of MWCS reduces random offset voltages to avoid transistor mismatch along with the reduced power dissipation due to low operating voltage. Here, the design simulation method includes Corner analysis for power consumption and Monte Carlo histogram analysis for transistor mismatch at different random offset voltages. All the design blocks were verified and simulated by Cadence’s virtuoso schematic editor with a TSMC model file at 45-nm technology by applying 500 mV and 1 V of the supply voltage. The proposed design has a transient power consumption of 41 nW, static power consumption of 17 nW, total delay of 1 ns, and power delay product (PDP) as 17 with a FOM of 1.83 (fJ/D). By using the proposed optimized design, a total of 80% power dissipation reduction was observed. Therefore, the proposed design is more efficient in terms of metrics like delay, power, and PDP at reduced offset voltage variations and reduced effect of process variations when compared to other existing comparators. The proposed comparator circuit is also simulated and verified through layout at 45-nm CMOS process technology.http://dx.doi.org/10.1155/jece/5040240 |
| spellingShingle | Tejender Singh Suman Lata Tripathi Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source Journal of Electrical and Computer Engineering |
| title | Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source |
| title_full | Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source |
| title_fullStr | Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source |
| title_full_unstemmed | Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source |
| title_short | Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source |
| title_sort | design and optimization of double tail dynamic latch cmos comparator with modified widlar current source |
| url | http://dx.doi.org/10.1155/jece/5040240 |
| work_keys_str_mv | AT tejendersingh designandoptimizationofdoubletaildynamiclatchcmoscomparatorwithmodifiedwidlarcurrentsource AT sumanlatatripathi designandoptimizationofdoubletaildynamiclatchcmoscomparatorwithmodifiedwidlarcurrentsource |