A Practical Cache Partitioning Method for Multi-Core Processor on a Commercial Safety-Critical Partitioned RTOS - Taeho Kim (IEEE Access)
In modern airborne systems, software plays a crucial role for meeting functional, safety, and performance requirements. Integrated Modular Avionics (IMA) and multi-core processors (MCPs) are also adopted for hardware to enhance performance and Space, Weight, and Power (SWaP). While MCPs improve efficiency, they introduce nondeterministic behaviors due to resource contention and challenges for the safety of avionics systems. This research proposes a practical cache partitioning method for commercial Real-Time Operating Systems (RTOS) on MCPs to reduce cache contention and enhance the safety and performance of avionics systems. A systematic procedure was developed based on DO-178 and CAST 32A to identify shared resources and prevent interference. Additionally, we developed a cache partitioning guide tool to decide the optimal cache partition for each application. This research demonstrated that shared L2 caches could cause severe performance degradation up to 88% using the WindRiver VxWorks 653 on the PowerPC T2080 processor. By applying the proposed partitioning technique, the system achieved 0% performance degradation, eliminating cache contention and ensuring consistent application performance. The partitioning approach also ensured deterministic application behavior, a critical requirement for safety-critical systems. Validation in a flight simulation environment confirmed the practicality of the method in real-world scenarios.