Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000
The subject of this paper is the analysis of DSP algorithm implementations based on HLS synthesis and SIMD instructions acceleration on the SoC hardware platform. The goal of this article is to analyze various FIR filter software and hardware implementations based on the technological platform SoC Z...
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National Aerospace University «Kharkiv Aviation Institute»
2024-11-01
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| Series: | Радіоелектронні і комп'ютерні системи |
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| Online Access: | http://nti.khai.edu/ojs/index.php/reks/article/view/2658 |
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| author | Olexander Shkil Oleh Filippenko Dariia Rakhlis Inna Filippenko Valentyn Korniienko |
| author_facet | Olexander Shkil Oleh Filippenko Dariia Rakhlis Inna Filippenko Valentyn Korniienko |
| author_sort | Olexander Shkil |
| collection | DOAJ |
| description | The subject of this paper is the analysis of DSP algorithm implementations based on HLS synthesis and SIMD instructions acceleration on the SoC hardware platform. The goal of this article is to analyze various FIR filter software and hardware implementations based on the technological platform SoC ZYNQ 7000 while obtaining metrics of hardware resource consumption, power efficiency, and execution performance. The tasks are as follows: determine the ways of implementing algorithms; choose the analysis criteria for multivariate experiment; implement algorithms using SIMD instructions on the ARM part of the given SoC; implement algorithms using High-Level Synthesis for the FPGA part; and measure and obtain the results for each signal topology. The used methods: High-Level Synthesis, optimization techniques based on vector instructions, and multivariate experiment analysis. The following results were obtained: for the given criteria and metrics. The FIR filter was implemented on the ZedBoard development platform with SoC ZYNQ 7000. The data were obtained from post-synthesis power analysis and dynamic SoC consumption using tools from Xilinx and Analog Devices. The corresponding IP blocks were implemented using High-Level Synthesis. The experiment was completed to obtain execution performance metrics. Conclusions. The scientific novelty of the obtained results is summarized as follows: the competitor analysis was performed for the set of implementations of the given algorithms deployed on the ZYNQ platform using both SIMD instructions and several HLS-based topologies for the FPGA-offload execution strategy. The analysis of the multivariate experiment was also completed for selected criteria, power consumption, filtering speed (inverse value – delay), and the amount of hardware costs as a percentage of the used resources. |
| format | Article |
| id | doaj-art-59ee069469f54b0986a4ea65057ff327 |
| institution | Kabale University |
| issn | 1814-4225 2663-2012 |
| language | English |
| publishDate | 2024-11-01 |
| publisher | National Aerospace University «Kharkiv Aviation Institute» |
| record_format | Article |
| series | Радіоелектронні і комп'ютерні системи |
| spelling | doaj-art-59ee069469f54b0986a4ea65057ff3272025-01-06T10:47:18ZengNational Aerospace University «Kharkiv Aviation Institute»Радіоелектронні і комп'ютерні системи1814-42252663-20122024-11-012024416817710.32620/reks.2024.4.142363Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000Olexander Shkil0Oleh Filippenko1Dariia Rakhlis2Inna Filippenko3Valentyn Korniienko4Kharkiv National University of Radio Electronics, KharkivKharkiv National University of Radio Electronics, KharkivKharkiv National University of Radio Electronics, KharkivKharkiv National University of Radio Electronics, KharkivKharkiv National University of Radio Electronics, KharkivThe subject of this paper is the analysis of DSP algorithm implementations based on HLS synthesis and SIMD instructions acceleration on the SoC hardware platform. The goal of this article is to analyze various FIR filter software and hardware implementations based on the technological platform SoC ZYNQ 7000 while obtaining metrics of hardware resource consumption, power efficiency, and execution performance. The tasks are as follows: determine the ways of implementing algorithms; choose the analysis criteria for multivariate experiment; implement algorithms using SIMD instructions on the ARM part of the given SoC; implement algorithms using High-Level Synthesis for the FPGA part; and measure and obtain the results for each signal topology. The used methods: High-Level Synthesis, optimization techniques based on vector instructions, and multivariate experiment analysis. The following results were obtained: for the given criteria and metrics. The FIR filter was implemented on the ZedBoard development platform with SoC ZYNQ 7000. The data were obtained from post-synthesis power analysis and dynamic SoC consumption using tools from Xilinx and Analog Devices. The corresponding IP blocks were implemented using High-Level Synthesis. The experiment was completed to obtain execution performance metrics. Conclusions. The scientific novelty of the obtained results is summarized as follows: the competitor analysis was performed for the set of implementations of the given algorithms deployed on the ZYNQ platform using both SIMD instructions and several HLS-based topologies for the FPGA-offload execution strategy. The analysis of the multivariate experiment was also completed for selected criteria, power consumption, filtering speed (inverse value – delay), and the amount of hardware costs as a percentage of the used resources.http://nti.khai.edu/ojs/index.php/reks/article/view/2658digital filtersdigital signal processing algorithmsaudio signalsembedded systemssocfpgaprogramming language chigh level synthesis |
| spellingShingle | Olexander Shkil Oleh Filippenko Dariia Rakhlis Inna Filippenko Valentyn Korniienko Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000 Радіоелектронні і комп'ютерні системи digital filters digital signal processing algorithms audio signals embedded systems soc fpga programming language c high level synthesis |
| title | Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000 |
| title_full | Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000 |
| title_fullStr | Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000 |
| title_full_unstemmed | Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000 |
| title_short | Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000 |
| title_sort | analysis of the implementation efficiency of digital signal processing systems on the technological platform soc zynq 7000 |
| topic | digital filters digital signal processing algorithms audio signals embedded systems soc fpga programming language c high level synthesis |
| url | http://nti.khai.edu/ojs/index.php/reks/article/view/2658 |
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