High-speed hardware architecture design and implementation of Ed25519 signature verification algorithm - Yiming XUE; Shurong LIU; Shuheng GUO; Yan LI; Cai’e HU (Tongxin xuebao)
Aiming at the high performance requirements of signature verification for specific scenarios such as blockchain, a high-speed hardware architecture of Ed25519 was proposed.To reduce the number of calculations for point addition and point double, a multiple point multiplication algorithm based on interleaving NAF was conducted by using pre-computation and lookup tables.The modular multiplication operation was realized by using the Karatsuba multiplication and fast reduction method, and the point addition and point double operation was designed without modular addition and subtraction, which could effectively improve the performance of point addition and point double.Given that modular exponentiation was the most time-consuming operation in the decompression process, a new modular exponentiation approach was developed by parallelizing modular inverse and modular multiplication, and therefore the performance of the de-compression operation could be improved.The proposed architecture fully considers the use of resources and is implemented on the Zynq-7020 FPGA platform with 13 695 slices, achieving 8 347 verifications per second at 81.6 MHz.