Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM
The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, desig...
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MDPI AG
2024-12-01
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| Series: | Energies |
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| Online Access: | https://www.mdpi.com/1996-1073/17/24/6349 |
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| author | Nermine M. Edward Sahar M. Hamed Wagdy R. Anis Nahla Elaraby |
| author_facet | Nermine M. Edward Sahar M. Hamed Wagdy R. Anis Nahla Elaraby |
| author_sort | Nermine M. Edward |
| collection | DOAJ |
| description | The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, designing robust SRAM cells that maintain stability and minimize power consumption is a key challenge. In this regard, with this ongoing work, the authors present novel designs of SRAMs using memristor technology by mitigating the shortcomings discussed above. This paper proposes a novel SRAM architecture of four transistors and five memristors, by integrating memristor technology to achieve drastic improvement in performance at subthreshold regions. Further, it performs an analysis of the metrics of static noise margin and power consumption to comprehensively evaluate the proposed SRAM designs. Simulation using Cadence Virtuoso for 65 nm technology demonstrates that power consumption for a 4T5M cell is about two and a half times lower than for 4T4M and 1.2 times lower than for 4T3M, hence proving that it will be promising for extremely low-power applications. |
| format | Article |
| id | doaj-art-4d1cea9b2a6648bb9aff9bf6cbca7fdd |
| institution | Kabale University |
| issn | 1996-1073 |
| language | English |
| publishDate | 2024-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Energies |
| spelling | doaj-art-4d1cea9b2a6648bb9aff9bf6cbca7fdd2024-12-27T14:23:33ZengMDPI AGEnergies1996-10732024-12-011724634910.3390/en17246349Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAMNermine M. Edward0Sahar M. Hamed1Wagdy R. Anis2Nahla Elaraby3Electronics and Communications Engineering Department, Ain Shams University, Cairo 11566, EgyptSchool of Engineering, Coventry University in Egypt, Cairo 11435, EgyptElectronics and Communications Engineering Department, Ain Shams University, Cairo 11566, EgyptInstitute of Computer Technology, Technical University of Vienna (TU Wien), 1040 Vienna, AustriaThe performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, designing robust SRAM cells that maintain stability and minimize power consumption is a key challenge. In this regard, with this ongoing work, the authors present novel designs of SRAMs using memristor technology by mitigating the shortcomings discussed above. This paper proposes a novel SRAM architecture of four transistors and five memristors, by integrating memristor technology to achieve drastic improvement in performance at subthreshold regions. Further, it performs an analysis of the metrics of static noise margin and power consumption to comprehensively evaluate the proposed SRAM designs. Simulation using Cadence Virtuoso for 65 nm technology demonstrates that power consumption for a 4T5M cell is about two and a half times lower than for 4T4M and 1.2 times lower than for 4T3M, hence proving that it will be promising for extremely low-power applications.https://www.mdpi.com/1996-1073/17/24/6349memristorSRAMlow power memoryCMOSMOS integrated circuit |
| spellingShingle | Nermine M. Edward Sahar M. Hamed Wagdy R. Anis Nahla Elaraby Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM Energies memristor SRAM low power memory CMOS MOS integrated circuit |
| title | Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM |
| title_full | Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM |
| title_fullStr | Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM |
| title_full_unstemmed | Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM |
| title_short | Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM |
| title_sort | towards efficient memory architectures low power noise immune rram |
| topic | memristor SRAM low power memory CMOS MOS integrated circuit |
| url | https://www.mdpi.com/1996-1073/17/24/6349 |
| work_keys_str_mv | AT nerminemedward towardsefficientmemoryarchitectureslowpowernoiseimmunerram AT saharmhamed towardsefficientmemoryarchitectureslowpowernoiseimmunerram AT wagdyranis towardsefficientmemoryarchitectureslowpowernoiseimmunerram AT nahlaelaraby towardsefficientmemoryarchitectureslowpowernoiseimmunerram |