Co-decode algorithm of network coding with hardware logic
Practical general coder and decoder of network coding(NC)with HDL(hardware description language)logic for wire-speed nodes was presented.The NC coders applied random linear network coding (RLNC) and the decoders recovered the original packets by Cramer’s rule.The structures and algorithms of NC code...
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| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | zho |
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Editorial Department of Journal on Communications
2012-07-01
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| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/zh/article/doi/1000-436X(2012)07-0001-08/ |
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| _version_ | 1841539900376088576 |
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| author | Hui LI Ming-long ZHANG Fu-xing CHEN Han-xu HOU Kai PAN Wei WANG Hu-sheng YUAN Tao SUN |
| author_facet | Hui LI Ming-long ZHANG Fu-xing CHEN Han-xu HOU Kai PAN Wei WANG Hu-sheng YUAN Tao SUN |
| author_sort | Hui LI |
| collection | DOAJ |
| description | Practical general coder and decoder of network coding(NC)with HDL(hardware description language)logic for wire-speed nodes was presented.The NC coders applied random linear network coding (RLNC) and the decoders recovered the original packets by Cramer’s rule.The structures and algorithms of NC coder and decoder were designed in detail and implemented in HDL with NetFPGA boards.Comparing with traditional stored-and-forward mechanism,network emulations showed that networks with wire-speed NC coder and decoder nodes could achieve the capacity bound of max-flow min-cut theorem,and the end-to-end delay was guaranteed on a small constant. |
| format | Article |
| id | doaj-art-4cb99a54a07141a5a16643cee84000d0 |
| institution | Kabale University |
| issn | 1000-436X |
| language | zho |
| publishDate | 2012-07-01 |
| publisher | Editorial Department of Journal on Communications |
| record_format | Article |
| series | Tongxin xuebao |
| spelling | doaj-art-4cb99a54a07141a5a16643cee84000d02025-01-14T06:32:15ZzhoEditorial Department of Journal on CommunicationsTongxin xuebao1000-436X2012-07-01331859663291Co-decode algorithm of network coding with hardware logicHui LIMing-long ZHANGFu-xing CHENHan-xu HOUKai PANWei WANGHu-sheng YUANTao SUNPractical general coder and decoder of network coding(NC)with HDL(hardware description language)logic for wire-speed nodes was presented.The NC coders applied random linear network coding (RLNC) and the decoders recovered the original packets by Cramer’s rule.The structures and algorithms of NC coder and decoder were designed in detail and implemented in HDL with NetFPGA boards.Comparing with traditional stored-and-forward mechanism,network emulations showed that networks with wire-speed NC coder and decoder nodes could achieve the capacity bound of max-flow min-cut theorem,and the end-to-end delay was guaranteed on a small constant.http://www.joconline.com.cn/zh/article/doi/1000-436X(2012)07-0001-08/network codingcoderdecoderNetFPGA |
| spellingShingle | Hui LI Ming-long ZHANG Fu-xing CHEN Han-xu HOU Kai PAN Wei WANG Hu-sheng YUAN Tao SUN Co-decode algorithm of network coding with hardware logic Tongxin xuebao network coding coder decoder NetFPGA |
| title | Co-decode algorithm of network coding with hardware logic |
| title_full | Co-decode algorithm of network coding with hardware logic |
| title_fullStr | Co-decode algorithm of network coding with hardware logic |
| title_full_unstemmed | Co-decode algorithm of network coding with hardware logic |
| title_short | Co-decode algorithm of network coding with hardware logic |
| title_sort | co decode algorithm of network coding with hardware logic |
| topic | network coding coder decoder NetFPGA |
| url | http://www.joconline.com.cn/zh/article/doi/1000-436X(2012)07-0001-08/ |
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