Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System

Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System

The open-source and customizable features of the RISC-V Instruction Set Architecture (ISA) have facilitated its rapid adoption since its publication in 2011. The availability of numerous free core designs leads to the pervasiveness of RISC-V-based devices on diverse applications spanning the Interne...

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Bibliographic Details
Main Authors: Binh Kieu-do-Nguyen, Khai-Duy Nguyen, Nguyen The Binh, Khai-Minh Ma, Tri-Duc Ta, Duc-Hung Le, Cong-Kha Pham, Trong-Thuc Hoang
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
RISC-V
multithread
multicore
task scheduling
hardware-software co-design
Online Access:https://ieeexplore.ieee.org/document/10767240/
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