Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System
The open-source and customizable features of the RISC-V Instruction Set Architecture (ISA) have facilitated its rapid adoption since its publication in 2011. The availability of numerous free core designs leads to the pervasiveness of RISC-V-based devices on diverse applications spanning the Interne...
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| Format: | Article |
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IEEE
2024-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10767240/ |
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| author | Binh Kieu-do-Nguyen Khai-Duy Nguyen Nguyen The Binh Khai-Minh Ma Tri-Duc Ta Duc-Hung Le Cong-Kha Pham Trong-Thuc Hoang |
| author_facet | Binh Kieu-do-Nguyen Khai-Duy Nguyen Nguyen The Binh Khai-Minh Ma Tri-Duc Ta Duc-Hung Le Cong-Kha Pham Trong-Thuc Hoang |
| author_sort | Binh Kieu-do-Nguyen |
| collection | DOAJ |
| description | The open-source and customizable features of the RISC-V Instruction Set Architecture (ISA) have facilitated its rapid adoption since its publication in 2011. The availability of numerous free core designs leads to the pervasiveness of RISC-V-based devices on diverse applications spanning the Internet of Things (IoT), embedded systems, artificial intelligence (AI), and virtual/augmented reality (VR/AR). The increasing prevalence of RISC-V cores has consequently caused a demand for high-performance and resource-efficient multicore systems. However, while numerous proposals exist for constructing multicore systems on conventional architectures, realizing an efficient multicore system that effectively leverages the features of RISC-V remains a challenge. This paper introduces a novel hardware/software co-design methodology to address these bottlenecks while minimizing resource utilization. Experimental results demonstrate the efficiency of our approach, exhibiting significant performance gains over single-threaded implementations and even surpassing traditional multi-threaded approaches. |
| format | Article |
| id | doaj-art-4996155d59894dc5aae703d8ade5e5d8 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-4996155d59894dc5aae703d8ade5e5d82024-12-04T00:00:36ZengIEEEIEEE Access2169-35362024-01-011217731217732610.1109/ACCESS.2024.350594010767240Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore SystemBinh Kieu-do-Nguyen0https://orcid.org/0000-0001-7240-7203Khai-Duy Nguyen1Nguyen The Binh2Khai-Minh Ma3Tri-Duc Ta4https://orcid.org/0000-0001-9458-012XDuc-Hung Le5https://orcid.org/0000-0003-3227-9117Cong-Kha Pham6https://orcid.org/0000-0001-5255-4919Trong-Thuc Hoang7https://orcid.org/0000-0002-4078-0836Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo, JapanDepartment of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo, JapanDepartment of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo, JapanDepartment of Electronics, Faculty of Electronics and Telecommunications, University of Science, Ho Chi Minh City, VietnamDepartment of Integrated Circuit and Hardware Design, Faculty of Computer Engineering, University of Information Technology, Ho Chi Minh City, VietnamDepartment of Electronics, Faculty of Electronics and Telecommunications, University of Science, Ho Chi Minh City, VietnamDepartment of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo, JapanDepartment of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo, JapanThe open-source and customizable features of the RISC-V Instruction Set Architecture (ISA) have facilitated its rapid adoption since its publication in 2011. The availability of numerous free core designs leads to the pervasiveness of RISC-V-based devices on diverse applications spanning the Internet of Things (IoT), embedded systems, artificial intelligence (AI), and virtual/augmented reality (VR/AR). The increasing prevalence of RISC-V cores has consequently caused a demand for high-performance and resource-efficient multicore systems. However, while numerous proposals exist for constructing multicore systems on conventional architectures, realizing an efficient multicore system that effectively leverages the features of RISC-V remains a challenge. This paper introduces a novel hardware/software co-design methodology to address these bottlenecks while minimizing resource utilization. Experimental results demonstrate the efficiency of our approach, exhibiting significant performance gains over single-threaded implementations and even surpassing traditional multi-threaded approaches.https://ieeexplore.ieee.org/document/10767240/RISC-Vmultithreadmulticoretask schedulinghardware-software co-design |
| spellingShingle | Binh Kieu-do-Nguyen Khai-Duy Nguyen Nguyen The Binh Khai-Minh Ma Tri-Duc Ta Duc-Hung Le Cong-Kha Pham Trong-Thuc Hoang Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System IEEE Access RISC-V multithread multicore task scheduling hardware-software co-design |
| title | Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System |
| title_full | Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System |
| title_fullStr | Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System |
| title_full_unstemmed | Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System |
| title_short | Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System |
| title_sort | hardware software co design for multi threaded computation on risc v based multicore system |
| topic | RISC-V multithread multicore task scheduling hardware-software co-design |
| url | https://ieeexplore.ieee.org/document/10767240/ |
| work_keys_str_mv | AT binhkieudonguyen hardwaresoftwarecodesignformultithreadedcomputationonriscvbasedmulticoresystem AT khaiduynguyen hardwaresoftwarecodesignformultithreadedcomputationonriscvbasedmulticoresystem AT nguyenthebinh hardwaresoftwarecodesignformultithreadedcomputationonriscvbasedmulticoresystem AT khaiminhma hardwaresoftwarecodesignformultithreadedcomputationonriscvbasedmulticoresystem AT triducta hardwaresoftwarecodesignformultithreadedcomputationonriscvbasedmulticoresystem AT duchungle hardwaresoftwarecodesignformultithreadedcomputationonriscvbasedmulticoresystem AT congkhapham hardwaresoftwarecodesignformultithreadedcomputationonriscvbasedmulticoresystem AT trongthuchoang hardwaresoftwarecodesignformultithreadedcomputationonriscvbasedmulticoresystem |