Efficient Implementation of DVI Protocol on FPGA

Efficient Implementation of DVI Protocol on FPGA

This paper presents a general-purpose hardware implementation of the digital visual interface (DVI) protocol on the Xilinx Virtex-6 ML605 FPGA platform for real-time display of digital processing results. The design enables direct output of processed data from the FPGA to an external monitor without...

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Bibliographic Details
Main Authors: Sara Ershadi-Nasab, Danial Bayati, Saeed Yazdani
Format: Article
Language:English
Published: Ferdowsi University of Mashhad 2025-05-01
Series:Computer and Knowledge Engineering
Subjects:
digital visual interface
field programmable gate array
image processing
real-time
video processing
xilinx virtex-6
Online Access:https://cke.um.ac.ir/article_46820_c1faf6e6187081fc6366184518ac7cb2.pdf
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Summary:This paper presents a general-purpose hardware implementation of the digital visual interface (DVI) protocol on the Xilinx Virtex-6 ML605 FPGA platform for real-time display of digital processing results. The design enables direct output of processed data from the FPGA to an external monitor without relying on external processors or software-based rendering tools. It addresses key challenges in timing synchronization, pixel formatting, and interfacing with the onboard Chrontel CH7301C encoder to support resolutions up to 1920×1080 at 60 Hz. A lightweight processing pipeline is developed in Verilog to convert multidimensional outputs into a sequential stream of pixel data conforming to the DVI protocol. As a case study, a lightweight convolutional neural network trained on the CIFAR-10 dataset is implemented on the FPGA, and its classification probabilities are displayed as a probability map on an LCD. Experimental results confirm low resource utilization and real-time performance, validating the system’s applicability in embedded applications such as machine learning inference, image processing, and real- time monitoring. This work demonstrates the feasibility of FPGA- based platforms for efficiently displaying digital video output in intelligent edge systems.
ISSN:2538-5453
2717-4123

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