Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit
This article proposed the use of an efficient ternary multiplexer as a building block in the implementation of ternary adders and multipliers. These designs aim to reduce the power consumption and minimize the transistor counts while maintaining low noise sensitivity. All ternary circuits use carbon...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2025-03-01
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| Series: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2772671125000191 |
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