Single-Path High-Resolution Digital PWM Architectures With Cascadability of Delay Lines
This paper introduces two new single-path and cascaded High-Resolution Digital Pulse Width Modulation (HRDPWM) architectures. The proposed single-path architecture uses fewer FPGA resources to achieve the same resolution as conventional dual-path architectures. Moreover, the generated HRDPWM signal...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Open Journal of Power Electronics |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10806584/ |
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