Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

In order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and bac...

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Bibliographic Details
Main Authors: Qian ZHANG, Ming ZHAN, Jianwu ZHANG, Fulong WANG, Yunkai1 FENG, Hao TANG
Format: Article
Language:zho
Published: Beijing Xintong Media Co., Ltd 2022-02-01
Series:Dianxin kexue
Subjects:
state measure merge calculation
Turbo code
FPGA implementation
parallel algorithm
Online Access:http://www.telecomsci.com/zh/article/doi/10.11959/j.issn.1000-0801.2022023/
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