Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations
In order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and bac...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | zho |
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Beijing Xintong Media Co., Ltd
2022-02-01
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| Series: | Dianxin kexue |
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| Online Access: | http://www.telecomsci.com/zh/article/doi/10.11959/j.issn.1000-0801.2022023/ |
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| _version_ | 1841529000472608768 |
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| author | Qian ZHANG Ming ZHAN Jianwu ZHANG Fulong WANG Yunkai1 FENG Hao TANG |
| author_facet | Qian ZHANG Ming ZHAN Jianwu ZHANG Fulong WANG Yunkai1 FENG Hao TANG |
| author_sort | Qian ZHANG |
| collection | DOAJ |
| description | In order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed, and effectiveness of the new architecture was demonstrated through field-programmable gate array (FPGA) hardware realization.The results show that, compared with the existing parallel Turbo decoder architectures, the proposed design architecture reduces the logic resource of state metrics calculation module about 50%, while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm. |
| format | Article |
| id | doaj-art-2fdf554f48c74b6a9e368b77d70ca0a6 |
| institution | Kabale University |
| issn | 1000-0801 |
| language | zho |
| publishDate | 2022-02-01 |
| publisher | Beijing Xintong Media Co., Ltd |
| record_format | Article |
| series | Dianxin kexue |
| spelling | doaj-art-2fdf554f48c74b6a9e368b77d70ca0a62025-01-15T03:26:39ZzhoBeijing Xintong Media Co., LtdDianxin kexue1000-08012022-02-0138475859809283Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculationsQian ZHANGMing ZHANJianwu ZHANGFulong WANGYunkai1 FENGHao TANGIn order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed, and effectiveness of the new architecture was demonstrated through field-programmable gate array (FPGA) hardware realization.The results show that, compared with the existing parallel Turbo decoder architectures, the proposed design architecture reduces the logic resource of state metrics calculation module about 50%, while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm.http://www.telecomsci.com/zh/article/doi/10.11959/j.issn.1000-0801.2022023/state measure merge calculationTurbo codeFPGA implementationparallel algorithm |
| spellingShingle | Qian ZHANG Ming ZHAN Jianwu ZHANG Fulong WANG Yunkai1 FENG Hao TANG Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations Dianxin kexue state measure merge calculation Turbo code FPGA implementation parallel algorithm |
| title | Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations |
| title_full | Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations |
| title_fullStr | Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations |
| title_full_unstemmed | Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations |
| title_short | Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations |
| title_sort | design and fpga implementation of an efficient parallel turbo decoder for combining state metric calculations |
| topic | state measure merge calculation Turbo code FPGA implementation parallel algorithm |
| url | http://www.telecomsci.com/zh/article/doi/10.11959/j.issn.1000-0801.2022023/ |
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