A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications - Sreenivasulu Polineni; Rekha S.; M. S. Bhat (IET Circuits, Devices and Systems)
Abstract A novel switched‐capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta‐sigma modulator (DSM) mode in 8‐bit to 15‐bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8‐bit to 15‐bit using a 3‐bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8‐bit to 11‐bit resolutions and as the first‐order DSM with a multi‐bit quantizer in 12‐bit to 15‐bit resolutions. The dynamic performance of the proposed ADC is verified through post‐layout simulations with a supply voltage of 1.8 V. It exhibits a signal‐to‐noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 μW across target resolutions (8–15 bits).