SAR-Assisted Energy-Efficient Hybrid ADCs
The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex...
Saved in:
Main Authors: | Kent Edrian Lozada, Dong-Jin Chang, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2024-01-01
|
Series: | IEEE Open Journal of the Solid-State Circuits Society |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/10702510/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS
by: Lucas Moura Santana, et al.
Published: (2025-01-01) -
DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation
by: Lizhen Zhang, et al.
Published: (2024-01-01) -
An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI
by: Bangda Yang, et al.
Published: (2025-01-01) -
Timing-Skew Calibration Techniques in Time-Interleaved ADCs
by: Mingyang Gu, et al.
Published: (2025-01-01) -
Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers
by: Seoyoung Jang, et al.
Published: (2024-01-01)