Research on <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub></math></inline-formula>-FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture
A quadratic extended-domain finely integrated operand scanning (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow>...
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| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
Editorial Department of Journal on Communications
2022-02-01
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| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/zh/article/doi/10.11959/j.issn.1000-436x.2022040/ |
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| Summary: | A quadratic extended-domain finely integrated operand scanning (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub> </math></inline-formula>-FIOS) modular multiplication algorithm for bilinear pairs was proposed to address the problem of low efficiency of bilinear pair operations.The algorithm effectively reduced the number of modular reductions in modular multiplication by optimizing the operation process of (AB+CD)mod P under the quadratic expansion domain.Two hardware architectures and their scheduling methods were designed to meet different application requirements.In order to improve the computational efficiency of the algorithm, the TSMC 55 nm process was used to realize the bilinear pairing operation unit.Compared with the existing literature, the designed architecture is superior to similar modular multiplication designs in performance indicators such as the first modular multiplication time, clock frequency and the area-time product, and also has certain advantages in the overall Optimal ate pair implementation. |
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| ISSN: | 1000-436X |