Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4
SQIsign is a well-known post-quantum signature scheme due to its small combined signature and public-key size. However, SQIsign suffers from notably long signing times, and verification times are not short either. To improve this, recent research has explored both one-dimensional and two-dimensiona...
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| Format: | Article |
| Language: | English |
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Ruhr-Universität Bochum
2024-12-01
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| Series: | Transactions on Cryptographic Hardware and Embedded Systems |
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| Online Access: | https://tosc.iacr.org/index.php/TCHES/article/view/11938 |
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| author | Marius A. Aardal Gora Adj Arwa Alblooshi Diego F. Aranha Isaac A. Canales-Martínez Jorge Chávez-Saab Décio Luiz Gazzoni Filho Krijn Reijnders Francisco Rodríguez-Henríquez |
| author_facet | Marius A. Aardal Gora Adj Arwa Alblooshi Diego F. Aranha Isaac A. Canales-Martínez Jorge Chávez-Saab Décio Luiz Gazzoni Filho Krijn Reijnders Francisco Rodríguez-Henríquez |
| author_sort | Marius A. Aardal |
| collection | DOAJ |
| description |
SQIsign is a well-known post-quantum signature scheme due to its small combined signature and public-key size. However, SQIsign suffers from notably long signing times, and verification times are not short either. To improve this, recent research has explored both one-dimensional and two-dimensional variants of SQIsign, each with distinct characteristics. In particular, SQIsign2D’s efficient signing and verification times have made it a focal point of recent research. However, the absence of an optimized one-dimensional verification implementation hampers a thorough comparison between these different variants. This work bridges this gap in the literature: we provide a state-of-the-art implementation of one-dimensional SQIsign verification, including novel optimizations. We report a record-breaking one-dimensional SQIsign verification time of 8.55 Mcycles on a Raptor Lake Intel processor, closely matching SQIsign2D on the same processor. For uncompressed signatures, the signature size doubles and we verify in only 5.6 Mcycles. Taking advantage of the inherent parallelism available in isogeny computations, we present 5-core variants that can go as low as 1.3 Mcycles. Furthermore, we present the first implementation that supports both 32-bit and 64-bit processors. It includes optimized assembly code for the Cortex-M4 and has been integrated with the pqm4 project. Our results motivate further research into one-dimensional SQIsign, as it boasts unique features among isogeny-based schemes.
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| format | Article |
| id | doaj-art-0e30e48d1b254596b11af416421837f3 |
| institution | Kabale University |
| issn | 2569-2925 |
| language | English |
| publishDate | 2024-12-01 |
| publisher | Ruhr-Universität Bochum |
| record_format | Article |
| series | Transactions on Cryptographic Hardware and Embedded Systems |
| spelling | doaj-art-0e30e48d1b254596b11af416421837f32024-12-09T16:49:06ZengRuhr-Universität BochumTransactions on Cryptographic Hardware and Embedded Systems2569-29252024-12-012025110.46586/tches.v2025.i1.497-522Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4Marius A. Aardal0Gora Adj1Arwa Alblooshi2Diego F. Aranha3Isaac A. Canales-Martínez4Jorge Chávez-Saab5Décio Luiz Gazzoni Filho6Krijn Reijnders7Francisco Rodríguez-Henríquez8Aarhus University, Aarhus, DenmarkCryptography Research Centre, Technology Innovation Institute, Abu Dhabi, UAECryptography Research Centre, Technology Innovation Institute, Abu Dhabi, UAEAarhus University, Aarhus, DenmarkCryptography Research Centre, Technology Innovation Institute, Abu Dhabi, UAECryptography Research Centre, Technology Innovation Institute, Abu Dhabi, UAEInstituto de Computação, Universidade Estadual de Campinas (UNICAMP), Campinas, Brazil; Department of Electrical Engineering, State University of Londrina, Londrina, BrazilRadboud University, Nijmegen, NetherlandsCryptography Research Centre, Technology Innovation Institute, Abu Dhabi, UAE SQIsign is a well-known post-quantum signature scheme due to its small combined signature and public-key size. However, SQIsign suffers from notably long signing times, and verification times are not short either. To improve this, recent research has explored both one-dimensional and two-dimensional variants of SQIsign, each with distinct characteristics. In particular, SQIsign2D’s efficient signing and verification times have made it a focal point of recent research. However, the absence of an optimized one-dimensional verification implementation hampers a thorough comparison between these different variants. This work bridges this gap in the literature: we provide a state-of-the-art implementation of one-dimensional SQIsign verification, including novel optimizations. We report a record-breaking one-dimensional SQIsign verification time of 8.55 Mcycles on a Raptor Lake Intel processor, closely matching SQIsign2D on the same processor. For uncompressed signatures, the signature size doubles and we verify in only 5.6 Mcycles. Taking advantage of the inherent parallelism available in isogeny computations, we present 5-core variants that can go as low as 1.3 Mcycles. Furthermore, we present the first implementation that supports both 32-bit and 64-bit processors. It includes optimized assembly code for the Cortex-M4 and has been integrated with the pqm4 project. Our results motivate further research into one-dimensional SQIsign, as it boasts unique features among isogeny-based schemes. https://tosc.iacr.org/index.php/TCHES/article/view/11938post-quantum cryptographyisogenySQIsignverificationARM |
| spellingShingle | Marius A. Aardal Gora Adj Arwa Alblooshi Diego F. Aranha Isaac A. Canales-Martínez Jorge Chávez-Saab Décio Luiz Gazzoni Filho Krijn Reijnders Francisco Rodríguez-Henríquez Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4 Transactions on Cryptographic Hardware and Embedded Systems post-quantum cryptography isogeny SQIsign verification ARM |
| title | Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4 |
| title_full | Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4 |
| title_fullStr | Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4 |
| title_full_unstemmed | Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4 |
| title_short | Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4 |
| title_sort | optimized one dimensional sqisign verification on intel and cortex m4 |
| topic | post-quantum cryptography isogeny SQIsign verification ARM |
| url | https://tosc.iacr.org/index.php/TCHES/article/view/11938 |
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