Translation lookaside buffer management
This paper focuses on the Translation Lookaside Buffer (TLB) management as part of memory management. TLB is an associative cache of the advanced processors, which reduces the overhead of the virtual to physical address translations. We consider challenges related to the design of the TLB management...
Saved in:
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Belarusian National Technical University
2019-12-01
|
| Series: | Системный анализ и прикладная информатика |
| Subjects: | |
| Online Access: | https://sapi.bntu.by/jour/article/view/416 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1849242706706956288 |
|---|---|
| author | Y. I. Klimiankou |
| author_facet | Y. I. Klimiankou |
| author_sort | Y. I. Klimiankou |
| collection | DOAJ |
| description | This paper focuses on the Translation Lookaside Buffer (TLB) management as part of memory management. TLB is an associative cache of the advanced processors, which reduces the overhead of the virtual to physical address translations. We consider challenges related to the design of the TLB management subsystem of the OS kernel on the example of the IA-32 platform and propose a simple model of complete and consistent policy of TLB management. This model can be used as a foundation for memory management subsystems design and verification. |
| format | Article |
| id | doaj-art-09f8e33c18f04a68b901075c5553d503 |
| institution | Kabale University |
| issn | 2309-4923 2414-0481 |
| language | English |
| publishDate | 2019-12-01 |
| publisher | Belarusian National Technical University |
| record_format | Article |
| series | Системный анализ и прикладная информатика |
| spelling | doaj-art-09f8e33c18f04a68b901075c5553d5032025-08-20T03:59:45ZengBelarusian National Technical UniversityСистемный анализ и прикладная информатика2309-49232414-04812019-12-0104202410.21122/2309-4923-2019-4-20-24311Translation lookaside buffer managementY. I. Klimiankou0Belarusian State University of Informatics and RadioelectronicsThis paper focuses on the Translation Lookaside Buffer (TLB) management as part of memory management. TLB is an associative cache of the advanced processors, which reduces the overhead of the virtual to physical address translations. We consider challenges related to the design of the TLB management subsystem of the OS kernel on the example of the IA-32 platform and propose a simple model of complete and consistent policy of TLB management. This model can be used as a foundation for memory management subsystems design and verification.https://sapi.bntu.by/jour/article/view/416virtual memoryphysical memorymemory managementtlb management |
| spellingShingle | Y. I. Klimiankou Translation lookaside buffer management Системный анализ и прикладная информатика virtual memory physical memory memory management tlb management |
| title | Translation lookaside buffer management |
| title_full | Translation lookaside buffer management |
| title_fullStr | Translation lookaside buffer management |
| title_full_unstemmed | Translation lookaside buffer management |
| title_short | Translation lookaside buffer management |
| title_sort | translation lookaside buffer management |
| topic | virtual memory physical memory memory management tlb management |
| url | https://sapi.bntu.by/jour/article/view/416 |
| work_keys_str_mv | AT yiklimiankou translationlookasidebuffermanagement |