VLSI architecture design of motion compensation for MPEG-4
In the light of complex control, high throughput and difficult implementation of motion compensation of MPEG-4 decoding, a motion compensation （MC） circuit solving the timing and I/O of decoding was presented for MPEG-4.The VLSI architecture and implementation in terms of VHDL were designed in the X...
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| Format: | Article |
| Language: | zho |
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Editorial Department of Journal on Communications
2005-01-01
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| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/zh/article/74668654/ |
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| _version_ | 1841537243531968512 |
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| author | LIU Long HAN Chong-zhao WANG Zhan-hui |
| author_facet | LIU Long HAN Chong-zhao WANG Zhan-hui |
| author_sort | LIU Long |
| collection | DOAJ |
| description | In the light of complex control, high throughput and difficult implementation of motion compensation of MPEG-4 decoding, a motion compensation （MC） circuit solving the timing and I/O of decoding was presented for MPEG-4.The VLSI architecture and implementation in terms of VHDL were designed in the Xilinx ISE6.1 i environment and some simulations were carried out in tools of electronic design automation （EDA）. The experimental results show that the VLSI processor designed can perform correct logic functions and can achieve a real-time coding for MPEG-4 Core Profile and Level 2. |
| format | Article |
| id | doaj-art-010119d1d67742af827537848e720a97 |
| institution | Kabale University |
| issn | 1000-436X |
| language | zho |
| publishDate | 2005-01-01 |
| publisher | Editorial Department of Journal on Communications |
| record_format | Article |
| series | Tongxin xuebao |
| spelling | doaj-art-010119d1d67742af827537848e720a972025-01-14T08:41:04ZzhoEditorial Department of Journal on CommunicationsTongxin xuebao1000-436X2005-01-0174668654VLSI architecture design of motion compensation for MPEG-4LIU LongHAN Chong-zhaoWANG Zhan-huiIn the light of complex control, high throughput and difficult implementation of motion compensation of MPEG-4 decoding, a motion compensation （MC） circuit solving the timing and I/O of decoding was presented for MPEG-4.The VLSI architecture and implementation in terms of VHDL were designed in the Xilinx ISE6.1 i environment and some simulations were carried out in tools of electronic design automation （EDA）. The experimental results show that the VLSI processor designed can perform correct logic functions and can achieve a real-time coding for MPEG-4 Core Profile and Level 2.http://www.joconline.com.cn/zh/article/74668654/very large scale integrated circuitMPEG-4Motion Compensation |
| spellingShingle | LIU Long HAN Chong-zhao WANG Zhan-hui VLSI architecture design of motion compensation for MPEG-4 Tongxin xuebao very large scale integrated circuit MPEG-4 Motion Compensation |
| title | VLSI architecture design of motion compensation for MPEG-4 |
| title_full | VLSI architecture design of motion compensation for MPEG-4 |
| title_fullStr | VLSI architecture design of motion compensation for MPEG-4 |
| title_full_unstemmed | VLSI architecture design of motion compensation for MPEG-4 |
| title_short | VLSI architecture design of motion compensation for MPEG-4 |
| title_sort | vlsi architecture design of motion compensation for mpeg 4 |
| topic | very large scale integrated circuit MPEG-4 Motion Compensation |
| url | http://www.joconline.com.cn/zh/article/74668654/ |
| work_keys_str_mv | AT liulong vlsiarchitecturedesignofmotioncompensationformpeg4 AT hanchongzhao vlsiarchitecturedesignofmotioncompensationformpeg4 AT wangzhanhui vlsiarchitecturedesignofmotioncompensationformpeg4 |