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Mountassar Maamoun
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Mountassar Maamoun
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Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
by
Mountassar Maamoun
,
Adnane Hassani
,
Samir Dahmani
,
Hocine Ait Saadi
,
Ghania Zerari
,
Noureddine Chabini
,
Rachid Beguenane
Published 2021-08-01
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